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| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-11-16 08:55:36 +0000 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-11-17 13:56:20 +0000 |
| commit | 118bb9fb5a62bb5a475b08b7b2f2c8346a230b1c (patch) | |
| tree | b463262439fb8b49a1fa045e8d0b82496d04c134 /drivers/gpu/drm/i915/i915_gem_tiling.c | |
| parent | 7ace3d302499652d5b850dbda4f49eb202bdd4b2 (diff) | |
| download | op-kernel-dev-118bb9fb5a62bb5a475b08b7b2f2c8346a230b1c.zip op-kernel-dev-118bb9fb5a62bb5a475b08b7b2f2c8346a230b1c.tar.gz | |
drm/i915: dev_priv cleanup in i915_gem_tiling.c
And a little bit of cascaded function prototype changes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 251d51b..c85e7b0 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -60,9 +60,9 @@ /* Check pitch constriants for all chips & tiling formats */ static bool -i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) +i915_tiling_ok(struct drm_i915_private *dev_priv, + int stride, int size, int tiling_mode) { - struct drm_i915_private *dev_priv = to_i915(dev); int tile_width; /* Linear is always fine */ @@ -81,10 +81,10 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) /* check maximum stride & object size */ /* i965+ stores the end address of the gtt mapping in the fence * reg, so dont bother to check the size */ - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) return false; - } else if (INTEL_INFO(dev)->gen >= 4) { + } else if (INTEL_GEN(dev_priv) >= 4) { if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) return false; } else { @@ -104,7 +104,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) return false; /* 965+ just needs multiples of tile width */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (stride & (tile_width - 1)) return false; return true; @@ -199,7 +199,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, if (!obj) return -ENOENT; - if (!i915_tiling_ok(dev, + if (!i915_tiling_ok(dev_priv, args->stride, obj->base.size, args->tiling_mode)) { i915_gem_object_put(obj); return -EINVAL; |
