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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-11-14 21:02:44 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-11-14 20:06:53 +0100 |
| commit | cf3d262e39941d8f148148e840c00fcbc35a8e6f (patch) | |
| tree | 3e3136d7f15a9d396ec26fee7ac4649bca4da1d5 /drivers/gpu/drm/i915/i915_gem_gtt.c | |
| parent | c2b66797cf34e4bc677c3a7cbb9ca5b1060031a1 (diff) | |
| download | op-kernel-dev-cf3d262e39941d8f148148e840c00fcbc35a8e6f.zip op-kernel-dev-cf3d262e39941d8f148148e840c00fcbc35a8e6f.tar.gz | |
drm/i915: Fix comments about CHV snoop behaviour
Replace the misinformed notes about CHV snoop behaviour with something
that's hopefully closer to reality.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 29a4486..2b00852 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1942,9 +1942,17 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) * Only the snoop bit has meaning for CHV, the rest is * ignored. * - * Note that the harware enforces snooping for all page - * table accesses. The snoop bit is actually ignored for - * PDEs. + * The hardware will never snoop for certain types of accesses: + * - CPU GTT (GMADR->GGTT->no snoop->memory) + * - PPGTT page tables + * - some other special cycles + * + * As with BDW, we also need to consider the following for GT accesses: + * "For GGTT, there is NO pat_sel[2:0] from the entry, + * so RTL will always use the value corresponding to + * pat_sel = 000". + * Which means we must set the snoop bit in PAT entry 0 + * in order to keep the global status page working. */ pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | GEN8_PPAT(1, 0) | |
