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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-04 18:42:07 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-11 20:42:53 +0000 |
| commit | 63256ec5347fb2344a42adbae732b90603c92f35 (patch) | |
| tree | 5b018e93f38f9e90f3b07beeaac4af08122c5876 /drivers/gpu/drm/i915/i915_gem_execbuffer.c | |
| parent | 759010728b1323aec03c5baae13fde8f76e44a99 (diff) | |
| download | op-kernel-dev-63256ec5347fb2344a42adbae732b90603c92f35.zip op-kernel-dev-63256ec5347fb2344a42adbae732b90603c92f35.tar.gz | |
drm/i915: Enforce write ordering through the GTT
We need to ensure that writes through the GTT land before any
modification to the MMIO registers and so must impose a mandatory write
barrier when flushing the GTT domain. This was revealed by relaxing the
write ordering by experimentally mapping the registers and the GATT as
write-combining.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_execbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 61129e6..0d42de4 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -725,6 +725,9 @@ i915_gem_execbuffer_flush(struct drm_device *dev, if (flush_domains & I915_GEM_DOMAIN_CPU) intel_gtt_chipset_flush(); + if (flush_domains & I915_GEM_DOMAIN_GTT) + wmb(); + if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { for (i = 0; i < I915_NUM_RINGS; i++) if (flush_rings & (1 << i)) |
