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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-11-03 14:15:13 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-11-03 16:17:57 -0700 |
| commit | 680da876f44a644aee891e1d0df5a560cfa4720e (patch) | |
| tree | 17c1789e558a33a71586f8310657555b9697247d /drivers/gpu/drm/i915/i915_gem.c | |
| parent | 4b9de737fad5bd8993e6070530802de22f32744d (diff) | |
| download | op-kernel-dev-680da876f44a644aee891e1d0df5a560cfa4720e.zip op-kernel-dev-680da876f44a644aee891e1d0df5a560cfa4720e.tar.gz | |
drm/i915: enable cacheable objects on Ivybridge
IVB supports these bits as well.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a838597..ed0b68f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3613,7 +3613,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU; - if (IS_GEN6(dev)) { + if (IS_GEN6(dev) || IS_GEN7(dev)) { /* On Gen6, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than |
