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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-03-20 08:09:19 +0200
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-03-20 08:13:50 +0200
commit17d5ca91cfc59ae91da5ff9da74ab09a9a2a17d9 (patch)
treea45f944e15a2600ec20ca4ec11b23d4641095e8e /drivers/gpu/drm/i915/i915_drv.h
parentb7e4ab50418d5b34ab0dae95193dd71190e1fb50 (diff)
parentc86907b59f505863ec7839471e889330982a596e (diff)
downloadop-kernel-dev-17d5ca91cfc59ae91da5ff9da74ab09a9a2a17d9.zip
op-kernel-dev-17d5ca91cfc59ae91da5ff9da74ab09a9a2a17d9.tar.gz
Merge branch '3.15/dss-dt' into 3.15/fbdev
Merge OMAP DSS DT support
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4a2bf8e..df77e20 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,6 +1831,14 @@ struct drm_i915_file_private {
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
+/*
+ * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
+ * even when in MSI mode. This results in spurious interrupt warnings if the
+ * legacy irq no. is shared with another device. The kernel then disables that
+ * interrupt source and so prevents the other device from working properly.
+ */
+#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
+#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
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