diff options
| author | Sonika Jindal <sonika.jindal@intel.com> | 2015-04-02 11:02:44 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-04-07 10:06:38 +0200 |
| commit | 474d1ec4a3d7775b071e60fdbe431cae37b84ff3 (patch) | |
| tree | 4a53aca8d67a522d82e69086ba04d33cfc294587 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | 2d1070b21e004609a5bebafdb4303bb021f5477c (diff) | |
| download | op-kernel-dev-474d1ec4a3d7775b071e60fdbe431cae37b84ff3.zip op-kernel-dev-474d1ec4a3d7775b071e60fdbe431cae37b84ff3.tar.gz | |
drm/i915/skl: Enabling PSR2 SU with frame sync
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to i915_psr
struct, add aux_frame_sync to independently control aux frame sync, rename the
TP2 TIME macro for 2500us (Rodrigo, Siva)
v3: Moving the resolution restriction to intel_psr_enable so that we check it
only once(Durga)
Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d63997b..1d62fbe 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -881,6 +881,8 @@ struct i915_psr { struct delayed_work work; unsigned busy_frontbuffer_bits; bool link_standby; + bool psr2_support; + bool aux_frame_sync; }; enum intel_pch { |
