diff options
| author | Dongwon Kim <dongwon.kim@intel.com> | 2015-09-17 11:26:35 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-23 15:36:58 +0200 |
| commit | 8204502a6aa2eab8cd5779020c2881fbc6361a96 (patch) | |
| tree | 9c5c9ee2e554348048329d8c5c4a78784b82f5ed /drivers/gpu/drm/i915/i915_dma.c | |
| parent | a2cad9dff4dd44d0244b966d980de9d602d87593 (diff) | |
| download | op-kernel-dev-8204502a6aa2eab8cd5779020c2881fbc6361a96.zip op-kernel-dev-8204502a6aa2eab8cd5779020c2881fbc6361a96.tar.gz | |
drm/i915: Do not hardcode s_max, ss_max and eu_mask for BXT
We can calculate BXT values correctly from GFX fuse values without
hardcoding special limits.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matthew D Roper <matthew.d.roper@intel.com>
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index c069550..817b05c 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -631,17 +631,6 @@ static void gen9_sseu_info_init(struct drm_device *dev) u32 fuse2, s_enable, ss_disable, eu_disable; u8 eu_mask = 0xff; - /* - * BXT has a single slice. BXT also has at most 6 EU per subslice, - * and therefore only the lowest 6 bits of the 8-bit EU disable - * fields are valid. - */ - if (IS_BROXTON(dev)) { - s_max = 1; - eu_max = 6; - eu_mask = 0x3f; - } - info = (struct intel_device_info *)&dev_priv->info; fuse2 = I915_READ(GEN8_FUSE2); s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> |
