diff options
| author | Changbin Du <changbin.du@intel.com> | 2017-03-30 11:32:05 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-03-30 17:47:39 +0800 |
| commit | f85726905745fb4f6e15c68e2ade9da5390f8d89 (patch) | |
| tree | 458386208689f2e0eea0dfc1cf1f2cbbe71e2202 /drivers/gpu/drm/i915/gvt | |
| parent | b79c52aef3cdee903017c1e9834b53996d70010e (diff) | |
| download | op-kernel-dev-f85726905745fb4f6e15c68e2ade9da5390f8d89.zip op-kernel-dev-f85726905745fb4f6e15c68e2ade9da5390f8d89.tar.gz | |
drm/i915/gvt: exclude cfg space from failsafe mode
When test GVTg as below scenario:
VM boot --> failsafe --> kill qemu --> VM boot.
Qemu report error at the second boot:
ERROR: PCI region size must be pow2 type=0x0, size=0x1fa1000
Qemu need access PCI_ROM_ADDRESS reg to determine the size of expansion
PCI rom. The mechanism just like the BAR reg (write-read) and we should
return the size 0 since we have no rom. If we reject the write to
PCI_ROM_ADDRESS, Qemu cannot get the correct size of rom.
Essentially, GVTg failsafe mode should not break PCI function. So we
exclude cfg space from failsafe mode. This can fix above issue.
v2: add Fixes and Bugzilla link.
Fixes: fd64be636708d ("drm/i915/gvt: introduced failsafe mode into vgpu")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100296
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/cfg_space.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index b7d7721..40af17e 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -285,9 +285,6 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, { int ret; - if (vgpu->failsafe) - return 0; - if (WARN_ON(bytes > 4)) return -EINVAL; |
