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authorTomasz Figa <tomasz.figa@gmail.com>2013-05-01 21:02:28 +0200
committerInki Dae <daeinki@gmail.com>2013-06-28 21:12:51 +0900
commit411d9ed4486a4e40bded42b2e026ba3ce866891f (patch)
tree671484b8b3fb90939180e2b7a52e245c4672227d /drivers/gpu/drm/exynos/exynos_drm_fimd.c
parentde7af1004bc74522d31675fdabdff432d2ddd986 (diff)
downloadop-kernel-dev-411d9ed4486a4e40bded42b2e026ba3ce866891f.zip
op-kernel-dev-411d9ed4486a4e40bded42b2e026ba3ce866891f.tar.gz
drm/exynos: fimd: Add support for FIMD variants with clock selection
Some platforms that can be supported this driver has additional clock source selection bits in VIDCON0 register that allows to select which clock should be used to drive the pixel clock: bus clock or special clock. Since this driver assumes that special clock always drives the pixel clock, this patch sets the selection bitfield to use the special clock. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_fimd.c')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 015a3be0..7681a8a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -65,6 +65,7 @@ struct fimd_driver_data {
unsigned int timing_base;
unsigned int has_shadowcon:1;
+ unsigned int has_clksel:1;
};
static struct fimd_driver_data exynos4_fimd_driver_data = {
@@ -278,6 +279,11 @@ static void fimd_commit(struct device *dev)
val = ctx->vidcon0;
val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
+ if (ctx->driver_data->has_clksel) {
+ val &= ~VIDCON0_CLKSEL_MASK;
+ val |= VIDCON0_CLKSEL_LCD;
+ }
+
if (ctx->clkdiv > 1)
val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
else
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