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author | Hyungwon Hwang <human.hwang@samsung.com> | 2015-06-12 21:59:03 +0900 |
---|---|---|
committer | Inki Dae <inki.dae@samsung.com> | 2015-06-22 20:05:00 +0900 |
commit | 26269af95af83145a3bccca41344c66502fdded9 (patch) | |
tree | 10d7d375f751e2a61cc1a9c0a51c4d6c07cb7ee0 /drivers/gpu/drm/exynos/exynos_drm_dsi.c | |
parent | 77bbd8914a91fab25f567772db60e2d1372de8c6 (diff) | |
download | op-kernel-dev-26269af95af83145a3bccca41344c66502fdded9.zip op-kernel-dev-26269af95af83145a3bccca41344c66502fdded9.tar.gz |
drm/exynos: dsi: rename pll_clk to sclk_clk
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly. But for the backward
compatibility, the old clock name "pll_clk" is also OK.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_dsi.c')
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_dsi.c | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index c1999ad..a3bfac2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -235,6 +235,8 @@ #define DSI_XFER_TIMEOUT_MS 100 #define DSI_RX_FIFO_EMPTY 0x30800002 +#define OLD_SCLK_MIPI_CLK_NAME "pll_clk" + enum exynos_dsi_transfer_type { EXYNOS_DSI_TX, EXYNOS_DSI_RX, @@ -279,7 +281,7 @@ struct exynos_dsi { void __iomem *reg_base; struct phy *phy; - struct clk *pll_clk; + struct clk *sclk_clk; struct clk *bus_clk; struct regulator_bulk_data supplies[2]; int irq; @@ -433,16 +435,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, u16 m; u32 reg; - clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate); - - fin = clk_get_rate(dsi->pll_clk); - if (!fin) { - dev_err(dsi->dev, "failed to get PLL clock frequency\n"); - return 0; - } - - dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin); - + fin = dsi->pll_clk_rate; fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); if (!fout) { dev_err(dsi->dev, @@ -1313,10 +1306,10 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi) goto err_bus_clk; } - ret = clk_prepare_enable(dsi->pll_clk); + ret = clk_prepare_enable(dsi->sclk_clk); if (ret < 0) { dev_err(dsi->dev, "cannot enable pll clock %d\n", ret); - goto err_pll_clk; + goto err_sclk_clk; } ret = phy_power_on(dsi->phy); @@ -1328,8 +1321,8 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi) return 0; err_phy: - clk_disable_unprepare(dsi->pll_clk); -err_pll_clk: + clk_disable_unprepare(dsi->sclk_clk); +err_sclk_clk: clk_disable_unprepare(dsi->bus_clk); err_bus_clk: regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); @@ -1355,7 +1348,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi) phy_power_off(dsi->phy); - clk_disable_unprepare(dsi->pll_clk); + clk_disable_unprepare(dsi->sclk_clk); clk_disable_unprepare(dsi->bus_clk); ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); @@ -1722,10 +1715,13 @@ static int exynos_dsi_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - dsi->pll_clk = devm_clk_get(dev, "pll_clk"); - if (IS_ERR(dsi->pll_clk)) { - dev_info(dev, "failed to get dsi pll input clock\n"); - return PTR_ERR(dsi->pll_clk); + dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi"); + if (IS_ERR(dsi->sclk_clk)) { + dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); + if (IS_ERR(dsi->sclk_clk)) { + dev_info(dev, "failed to get dsi sclk clock\n"); + eturn PTR_ERR(dsi->sclk_clk); + } } dsi->bus_clk = devm_clk_get(dev, "bus_clk"); |