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authorAndy Lutomirski <luto@amacapital.net>2013-05-13 23:58:43 +0000
committerDave Airlie <airlied@redhat.com>2013-05-31 13:37:31 +1000
commitf435046d38af631920b299455db9e95dfc06d055 (patch)
tree34ed84a701acbb024af166e553743901f0b29cc1 /drivers/gpu/drm/drm_pci.c
parentff47eaf24d01b5753e4964b10c606e0d711b143e (diff)
downloadop-kernel-dev-f435046d38af631920b299455db9e95dfc06d055.zip
op-kernel-dev-f435046d38af631920b299455db9e95dfc06d055.tar.gz
drm, agpgart: Use pgprot_writecombine for AGP maps and make the MTRR optional
I'm not sure I understand the intent of the previous behavior. mmap on /dev/agpgart and DRM_AGP maps had no cache flags set, so they would be fully cacheable. But the DRM code (most of the time) would add a write-combining MTRR that would change the effective memory type to WC. The new behavior just requests WC explicitly for all AGP maps. If there is any code out there that expects cacheable access to the AGP aperture (because the drm driver doesn't request an MTRR or because it's using /dev/agpgart directly), then it will now end up with a UC or WC mapping, depending on the architecture and PAT availability. But cacheable access to the aperture seems like it's asking for trouble, because, AIUI, the aperture is an alias of RAM. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Andy Lutomirski <luto@amacapital.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/drm_pci.c')
-rw-r--r--drivers/gpu/drm/drm_pci.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 14194b6..80c0b2b 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -278,10 +278,10 @@ static int drm_pci_agp_init(struct drm_device *dev)
}
if (drm_core_has_MTRR(dev)) {
if (dev->agp)
- dev->agp->agp_mtrr =
- mtrr_add(dev->agp->agp_info.aper_base,
- dev->agp->agp_info.aper_size *
- 1024 * 1024, MTRR_TYPE_WRCOMB, 1);
+ dev->agp->agp_mtrr = arch_phys_wc_add(
+ dev->agp->agp_info.aper_base,
+ dev->agp->agp_info.aper_size *
+ 1024 * 1024);
}
}
return 0;
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