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| author | Alex Deucher <alexander.deucher@amd.com> | 2016-04-29 11:20:32 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-04 20:30:44 -0400 |
| commit | bdf1ecea3c656acab45976ff7a6ba53b37cd7a1d (patch) | |
| tree | b8a08117402868a3760d1e4b56b8faa4a6d0743b /drivers/gpu/drm/amd/powerplay | |
| parent | ce90dbd9b844212a9326cbeed8013abee5ac46d2 (diff) | |
| download | op-kernel-dev-bdf1ecea3c656acab45976ff7a6ba53b37cd7a1d.zip op-kernel-dev-bdf1ecea3c656acab45976ff7a6ba53b37cd7a1d.tar.gz | |
drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2)
Need to call the IP cg callbacks.
v2: fix gate logic
Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c index e68edf0..e1b649b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c @@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) data->uvd_power_gated = bgate; - if (bgate) + if (bgate) { + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_GATE); fiji_update_uvd_dpm(hwmgr, true); - else + } else { fiji_update_uvd_dpm(hwmgr, false); + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_UNGATE); + } return 0; } |
