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| author | Rex Zhu <Rex.Zhu@amd.com> | 2017-09-20 17:18:16 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 15:14:32 -0400 |
| commit | a9eca3a685b9fc3c9910eca4783ef07a2345b9e0 (patch) | |
| tree | f5b00fa1bb433a2088afaf0e62c5558042f3ac6d /drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | |
| parent | fbabae46964fec421c717d27b57d4383e8ae4b64 (diff) | |
| download | op-kernel-dev-a9eca3a685b9fc3c9910eca4783ef07a2345b9e0.zip op-kernel-dev-a9eca3a685b9fc3c9910eca4783ef07a2345b9e0.tar.gz | |
drm/amd/powerplay: delete SMUM_WRITE_FIELD
the macro is as same as PHM_WRITE_FIELD
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c index 0f23e23..af5c4d3 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c @@ -40,7 +40,7 @@ static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr); - SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */ return 0; } @@ -506,12 +506,12 @@ static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000); - SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1); for (; byte_count >= 4; byte_count -= 4) cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++); - SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); + PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL); |
