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author | Flora Cui <Flora.Cui@amd.com> | 2016-03-14 18:33:29 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-04 20:27:57 -0400 |
commit | 2cc0c0b5cd4d07a65267c28a4f7b68134abff472 (patch) | |
tree | 6f989d1e7fb5706e171c08881720ba8da8734bfc /drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h | |
parent | a3ad7a9ad8ef2e87ffa7e65d6ce0e9928b4134e9 (diff) | |
download | op-kernel-dev-2cc0c0b5cd4d07a65267c28a4f7b68134abff472.zip op-kernel-dev-2cc0c0b5cd4d07a65267c28a4f7b68134abff472.tar.gz |
drm/amdgpu: change ELM/BAF to Polaris10/Polaris11
Adjust to preferred code names.
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h index f816262..f6a7591 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h @@ -705,6 +705,7 @@ struct SMU7_Discrete_Pm_Status_Table { uint16_t Sclk_dpm_residency[8]; uint16_t Uvd_dpm_residency[8]; uint16_t Vce_dpm_residency[8]; + uint16_t Mclk_dpm_residency[4]; uint32_t P_vddci_acc; uint32_t P_vddr1_acc; @@ -779,6 +780,47 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 +// DIDT Defines +#define SQ_Enable_MASK 0x1 +#define SQ_IR_MASK 0x2 +#define SQ_PCC_MASK 0x4 +#define SQ_EDC_MASK 0x8 + +#define TCP_Enable_MASK 0x100 +#define TCP_IR_MASK 0x200 +#define TCP_PCC_MASK 0x400 +#define TCP_EDC_MASK 0x800 + +#define TD_Enable_MASK 0x10000 +#define TD_IR_MASK 0x20000 +#define TD_PCC_MASK 0x40000 +#define TD_EDC_MASK 0x80000 + +#define DB_Enable_MASK 0x1000000 +#define DB_IR_MASK 0x2000000 +#define DB_PCC_MASK 0x4000000 +#define DB_EDC_MASK 0x8000000 + +#define SQ_Enable_SHIFT 0 +#define SQ_IR_SHIFT 1 +#define SQ_PCC_SHIFT 2 +#define SQ_EDC_SHIFT 3 + +#define TCP_Enable_SHIFT 8 +#define TCP_IR_SHIFT 9 +#define TCP_PCC_SHIFT 10 +#define TCP_EDC_SHIFT 11 + +#define TD_Enable_SHIFT 16 +#define TD_IR_SHIFT 17 +#define TD_PCC_SHIFT 18 +#define TD_EDC_SHIFT 19 + +#define DB_Enable_SHIFT 24 +#define DB_IR_SHIFT 25 +#define DB_PCC_SHIFT 26 +#define DB_EDC_SHIFT 27 + #pragma pack(pop) |