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| author | Tom St Denis <tom.stdenis@amd.com> | 2017-09-08 09:45:34 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-12 14:32:36 -0400 |
| commit | 298e87c95f9c8c2f33d274e92568c6b83ac999a5 (patch) | |
| tree | 0aebc597900892c1a734d799567c731a038716de /drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | |
| parent | 23db59e48aa8e5eb622afd9f698e5263fb72c464 (diff) | |
| download | op-kernel-dev-298e87c95f9c8c2f33d274e92568c6b83ac999a5.zip op-kernel-dev-298e87c95f9c8c2f33d274e92568c6b83ac999a5.tar.gz | |
drm/amd/powerplay: Tidy up vega10_thermal_initialize()
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c index d5d6765..5b3c443 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c @@ -429,19 +429,16 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) reg = soc15_get_register_offset(THM_HWID, 0, mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_TACH_CTRL__EDGE_PER_REV_MASK) | - ((hwmgr->thermal_controller.fanInfo. - ucTachometerPulsesPerRevolution - 1) << - CG_TACH_CTRL__EDGE_PER_REV__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_TACH_CTRL, EDGE_PER_REV, + hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1)); } reg = soc15_get_register_offset(THM_HWID, 0, mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2); cgs_write_register(hwmgr->device, reg, - (cgs_read_register(hwmgr->device, reg) & - ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) | - (0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT)); + CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg), + CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28)); return 0; } |
