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| author | Alex Deucher <alexander.deucher@amd.com> | 2015-11-11 20:18:52 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2015-12-21 16:42:30 -0500 |
| commit | 16881da6c0b9db5fca95b96b0f02720e94c92629 (patch) | |
| tree | e8d219593c42cbad730938bd66f4151c4aa1e695 /drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h | |
| parent | 74c577b0313d4140ec8b61745c6ade3a4d735d33 (diff) | |
| download | op-kernel-dev-16881da6c0b9db5fca95b96b0f02720e94c92629.zip op-kernel-dev-16881da6c0b9db5fca95b96b0f02720e94c92629.tar.gz | |
drm/amdgpu: extract pcie helpers to common header
These will be used by multiple powerplay drivers and
other IP modules.
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h index 44b985a..49168d2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h @@ -386,30 +386,6 @@ typedef struct tonga_hwmgr tonga_hwmgr; #define TONGA_UNUSED_GPIO_PIN 0x7F -/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */ -#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000 -#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000 -#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000 -#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000 -#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16 - -/* Following flags shows PCIe link speed supported by ASIC H/W.*/ -#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001 -#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002 -#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004 -#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF -#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0 - -/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */ -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000 -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000 -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000 -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000 -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000 -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000 -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000 -#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16 - #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X) #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X) |
