Merge branch 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux into drm-next

Some additional fixes for 4.9:
- The rest of Christian's GTT rework which fixes a long standing bug
  in the GPUVM code among other things
- Changes to the pci shutdown callbacks for certain hypervisors
- Fix hpd interrupt storms on eDP panels which have the hpd interrupt
  enabled by the bios
- misc cleanups and bug fixes

* 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux: (33 commits)
  drm/radeon: always apply pci shutdown callbacks
  drm/amdgpu: always apply pci shutdown callbacks (v2)
  drm/amdgpu: improve VM PTE trace points
  drm/amdgpu: fix GART_DEBUGFS define
  drm/amdgpu: free userptrs even if GTT isn't bound
  drm/amd/amdgpu: Various cleanups for DCEv6
  drm/amdgpu: fix BO move offsets
  drm/amdgpu: fix amdgpu_move_blit on 32bit systems
  drm/amdgpu: fix gtt_mgr bo's offset
  drm/amdgpu: fix initializing the VM BO shadow
  drm/amdgpu: fix initializing the VM last eviction counter
  drm/amdgpu: cleanup VM shadow BO unreferencing
  drm/amdgpu: allocate GTT space for shadow VM page tables
  drm/amdgpu: rename all rbo variable to abo v2
  drm/amdgpu: remove unused member from struct amdgpu_bo
  drm/amdgpu: add a custom GTT memory manager v2
  drm/amdgpu/dce6: disable hpd on local panels
  drm/amdgpu/dce8: disable hpd on local panels
  drm/amdgpu/dce11: disable hpd on local panels
  drm/amdgpu/dce10: disable hpd on local panels
  ...

1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 260fce050..41b634f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -31,7 +31,7 @@
 
 static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
 
-static struct gpu_pt_config_reg GCCACConfig_Polaris10[] = {
+static const struct gpu_pt_config_reg GCCACConfig_Polaris10[] = {
 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  *      Offset                             Mask                                                Shift                                               Value       Type
  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -62,7 +62,7 @@ static struct gpu_pt_config_reg GCCACConfig_Polaris10[] = {
 	{   0xFFFFFFFF  }
 };
 
-static struct gpu_pt_config_reg GCCACConfig_Polaris11[] = {
+static const struct gpu_pt_config_reg GCCACConfig_Polaris11[] = {
 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  *      Offset                             Mask                                                Shift                                               Value       Type
  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -93,7 +93,7 @@ static struct gpu_pt_config_reg GCCACConfig_Polaris11[] = {
 	{   0xFFFFFFFF  }
 };
 
-static struct gpu_pt_config_reg DIDTConfig_Polaris10[] = {
+static const struct gpu_pt_config_reg DIDTConfig_Polaris10[] = {
 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  *      Offset                             Mask                                                Shift                                               Value       Type
  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -235,7 +235,7 @@ static struct gpu_pt_config_reg DIDTConfig_Polaris10[] = {
 	{   0xFFFFFFFF  }
 };
 
-static struct gpu_pt_config_reg DIDTConfig_Polaris11[] = {
+static const struct gpu_pt_config_reg DIDTConfig_Polaris11[] = {
 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  *      Offset                             Mask                                                Shift                                               Value       Type
  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -427,9 +427,9 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
 }
 
 static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr,
-				struct gpu_pt_config_reg *cac_config_regs)
+				const struct gpu_pt_config_reg *cac_config_regs)
 {
-	struct gpu_pt_config_reg *config_regs = cac_config_regs;
+	const struct gpu_pt_config_reg *config_regs = cac_config_regs;
 	uint32_t cache = 0;
 	uint32_t data = 0;