diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2015-11-24 17:42:02 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2015-12-02 15:54:18 -0500 |
| commit | aa5e24e5f8a83b19b1b19964f35562c7a42636e2 (patch) | |
| tree | b63adb9ee21e85561dbb7da1a0cfd178c7cd9c49 /drivers/gpu/drm/amd/include | |
| parent | 623fc3b7bdbfd64536576f71f87652385d4d88fc (diff) | |
| download | op-kernel-dev-aa5e24e5f8a83b19b1b19964f35562c7a42636e2.zip op-kernel-dev-aa5e24e5f8a83b19b1b19964f35562c7a42636e2.tar.gz | |
drm/amd: add new gfx8 register definitions for EDC
EDC is a RAS feature for on chip memory.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h index daf763b..a9b6923 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h @@ -2807,5 +2807,18 @@ #define ixDIDT_DBR_WEIGHT0_3 0x90 #define ixDIDT_DBR_WEIGHT4_7 0x91 #define ixDIDT_DBR_WEIGHT8_11 0x92 +#define mmTD_EDC_CNT 0x252e +#define mmCPF_EDC_TAG_CNT 0x3188 +#define mmCPF_EDC_ROQ_CNT 0x3189 +#define mmCPF_EDC_ATC_CNT 0x318a +#define mmCPG_EDC_TAG_CNT 0x318b +#define mmCPG_EDC_ATC_CNT 0x318c +#define mmCPG_EDC_DMA_CNT 0x318d +#define mmCPC_EDC_SCRATCH_CNT 0x318e +#define mmCPC_EDC_UCODE_CNT 0x318f +#define mmCPC_EDC_ATC_CNT 0x3190 +#define mmDC_EDC_STATE_CNT 0x3191 +#define mmDC_EDC_CSINVOC_CNT 0x3192 +#define mmDC_EDC_RESTORE_CNT 0x3193 #endif /* GFX_8_0_D_H */ |
