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| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2018-03-12 18:25:15 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-21 14:36:53 -0500 |
| commit | 3084eb0011b38cceaafb9312ad90fe20d343daa7 (patch) | |
| tree | 14ed8f0fe5f86252809ba73390988ab382c6da3a /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | f559fe2bc1c1c338e5e9f4fa04e2ab12e59d1818 (diff) | |
| download | op-kernel-dev-3084eb0011b38cceaafb9312ad90fe20d343daa7.zip op-kernel-dev-3084eb0011b38cceaafb9312ad90fe20d343daa7.tar.gz | |
drm/amdgpu/soc15: initialize reg base for vega12
Initialize the IP offsets for vega12.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index e308c3c..51cf8a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -508,6 +508,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) /* Set IP register base before any HW register access */ switch (adev->asic_type) { case CHIP_VEGA10: + case CHIP_VEGA12: case CHIP_RAVEN: vega10_reg_base_init(adev); break; |
