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authorChristian König <christian.koenig@amd.com>2017-12-05 15:23:26 +0100
committerAlex Deucher <alexander.deucher@amd.com>2017-12-18 11:53:08 -0500
commit6a42fd6fbf5340968b1fb41bf6a700699ddb5a13 (patch)
tree74dfd606da7c32930dd82271a8853802a36e685c /drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
parent78f99c6d5c8ea707cf1953aaa73b911679f9066a (diff)
downloadop-kernel-dev-6a42fd6fbf5340968b1fb41bf6a700699ddb5a13.zip
op-kernel-dev-6a42fd6fbf5340968b1fb41bf6a700699ddb5a13.tar.gz
drm/amdgpu: implement 2+1 PD support for Raven v3
Instead of falling back to 2 level and very limited address space use 2+1 PD support and 128TB + 512GB of virtual address space. v2: cleanup defines, rebase on top of level enum v3: fix inverted check in hardware setup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 1056484..edd2ea52 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -70,6 +70,12 @@ struct amdgpu_bo_list_entry;
/* PDE is handled as PTE for VEGA10 */
#define AMDGPU_PDE_PTE (1ULL << 54)
+/* PTE is handled as PDE for VEGA10 (Translate Further) */
+#define AMDGPU_PTE_TF (1ULL << 56)
+
+/* PDE Block Fragment Size for VEGA10 */
+#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
+
/* VEGA10 only */
#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
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