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authorLaxman Dewangan <ldewangan@nvidia.com>2016-02-22 17:43:28 +0530
committerLaxman Dewangan <ldewangan@nvidia.com>2016-02-23 20:35:37 +0530
commit00b9ab4a25cf5a4527cf6c8adb415caa4f05ed3d (patch)
treed04a08b15ceccc3ad8d2391266ec93d7429962e5 /drivers/gpio/gpio-mvebu.c
parent33bde5c503834439231df6ff3b8a17b724dbca70 (diff)
downloadop-kernel-dev-00b9ab4a25cf5a4527cf6c8adb415caa4f05ed3d.zip
op-kernel-dev-00b9ab4a25cf5a4527cf6c8adb415caa4f05ed3d.tar.gz
gpio: mvebu: Use devm_gpiochip_add_data() for gpio registration
Use devm_gpiochip_add_data() for GPIO registration and clean the error path. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers/gpio/gpio-mvebu.c')
-rw-r--r--drivers/gpio/gpio-mvebu.c11
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index a5eacc1..11c6582 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -756,7 +756,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
BUG();
}
- gpiochip_add_data(&mvchip->chip, mvchip);
+ devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
/* Some gpio controllers do not provide irq support */
if (!of_irq_count(np))
@@ -777,16 +777,14 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
if (mvchip->irqbase < 0) {
dev_err(&pdev->dev, "no irqs\n");
- err = mvchip->irqbase;
- goto err_gpiochip_add;
+ return mvchip->irqbase;
}
gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
mvchip->membase, handle_level_irq);
if (!gc) {
dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
- err = -ENOMEM;
- goto err_gpiochip_add;
+ return -ENOMEM;
}
gc->private = mvchip;
@@ -828,9 +826,6 @@ err_generic_chip:
IRQ_LEVEL | IRQ_NOPROBE);
kfree(gc);
-err_gpiochip_add:
- gpiochip_remove(&mvchip->chip);
-
return err;
}
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