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| author | Stefan Richter <stefanr@s5r6.in-berlin.de> | 2007-08-25 14:08:19 +0200 |
|---|---|---|
| committer | Stefan Richter <stefanr@s5r6.in-berlin.de> | 2007-10-17 00:00:05 +0200 |
| commit | ee71c2f9ee85117e41ef87357ed8f75d29369b98 (patch) | |
| tree | 9bb749909370ec732ed730ca80553908913156af /drivers/firewire | |
| parent | df8ec2490fed5dd23316bbb2c2e90e59e7d37126 (diff) | |
| download | op-kernel-dev-ee71c2f9ee85117e41ef87357ed8f75d29369b98.zip op-kernel-dev-ee71c2f9ee85117e41ef87357ed8f75d29369b98.tar.gz | |
firewire: fw-ohci: enforce read order for selfID generation
It seems unlikely, but access to self_id_cpu[0] could at least in theory
be deferred until after the loop over self_id_cpu[1..n] or even after
the subsequent reg_read. Enforce the desired order by a read barrier.
Also prevent the reg_read from being reordered relative to the for loop.
This isn't necessary if the loop's conditional printk counts as an
implicit barrier, but better make it explicit.
(self_id_cpu[] is a coherent DMA buffer.)
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Diffstat (limited to 'drivers/firewire')
| -rw-r--r-- | drivers/firewire/fw-ohci.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/fw-ohci.c index e14c1ca7..a7947ba 100644 --- a/drivers/firewire/fw-ohci.c +++ b/drivers/firewire/fw-ohci.c @@ -30,6 +30,7 @@ #include <asm/uaccess.h> #include <asm/semaphore.h> +#include <asm/system.h> #include "fw-transaction.h" #include "fw-ohci.h" @@ -926,12 +927,14 @@ static void bus_reset_tasklet(unsigned long data) self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; + rmb(); for (i = 1, j = 0; j < self_id_count; i += 2, j++) { if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) fw_error("inconsistent self IDs\n"); ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); } + rmb(); /* * Check the consistency of the self IDs we just read. The |
