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authorMauro Carvalho Chehab <mchehab@redhat.com>2010-08-26 23:19:54 -0300
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-08-30 14:56:45 -0300
commit116389ed21e4ad88f65e7ec5ed6ca224acb89115 (patch)
tree2e891ce607811b12b8be1ab1c9d69a3a2e3b98c1 /drivers/edac
parentc3af2eaf7a3257f7b44165ec487215574c47fd32 (diff)
downloadop-kernel-dev-116389ed21e4ad88f65e7ec5ed6ca224acb89115.zip
op-kernel-dev-116389ed21e4ad88f65e7ec5ed6ca224acb89115.tar.gz
i7300_edac: Add a FIXME note about the error correction type
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/i7300_edac.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index 7e035b6..36265e2 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -841,6 +841,15 @@ static int decode_mtr(struct i7300_pvt *pvt,
p_csrow->grain = 8;
p_csrow->nr_pages = dinfo->megabytes << 8;
p_csrow->mtype = MEM_FB_DDR2;
+
+ /*
+ * FIXME: the type of error detection actually depends of the
+ * mode of operation. When it is just one single memory chip, at
+ * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
+ * In normal or mirrored mode, it uses Single Device Data correction,
+ * with the possibility of using an extended algorithm for x8 memories
+ * See datasheet Sections 7.3.6 to 7.3.8
+ */
p_csrow->edac_mode = EDAC_S8ECD8ED;
/* ask what device type on this row */
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