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authorDaniel Mack <zonque@gmail.com>2013-08-10 18:52:15 +0200
committerVinod Koul <vinod.koul@intel.com>2013-08-14 13:55:15 +0530
commit8b298ded902a96cf434738d2a1d83f4a768362ea (patch)
treea3c5c92c8e0fbf98ac62a680a82d8e838fbe742f /drivers/dma
parentaab81e47f58ea13f8bf7c1046670dd80566b1040 (diff)
downloadop-kernel-dev-8b298ded902a96cf434738d2a1d83f4a768362ea.zip
op-kernel-dev-8b298ded902a96cf434738d2a1d83f4a768362ea.tar.gz
dma: mmp_pdma: factor out DRCMR register calculation
The exact same calculation is done twice, so let's factor it out to a macro. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/mmp_pdma.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
index 3bf9c91..b061e26 100644
--- a/drivers/dma/mmp_pdma.c
+++ b/drivers/dma/mmp_pdma.c
@@ -47,6 +47,8 @@
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_EORINTR (1 << 9) /* The end of Receive */
+#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + \
+ (((n) & 0x3f) << 2))
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
@@ -143,8 +145,7 @@ static void enable_chan(struct mmp_pdma_phy *phy)
if (!phy->vchan)
return;
- reg = phy->vchan->drcmr;
- reg = (((reg) < 64) ? 0x0100 : 0x1100) + (((reg) & 0x3f) << 2);
+ reg = DRCMR(phy->vchan->drcmr);
writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
reg = (phy->idx << 2) + DCSR;
@@ -258,8 +259,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan)
return;
/* clear the channel mapping in DRCMR */
- reg = pchan->phy->vchan->drcmr;
- reg = ((reg < 64) ? 0x0100 : 0x1100) + ((reg & 0x3f) << 2);
+ reg = DRCMR(pchan->phy->vchan->drcmr);
writel(0, pchan->phy->base + reg);
spin_lock_irqsave(&pdev->phy_lock, flags);
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