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authorLinus Walleij <linus.walleij@stericsson.com>2010-06-20 21:24:52 +0000
committerDan Williams <dan.j.williams@intel.com>2010-06-22 18:01:53 -0700
commitef1872ec652b3bc472d6c0995d0b64d5058878ea (patch)
tree2de7cbca0012ab6931b8321c922311f70bbb4bb0 /drivers/dma/ste_dma40_ll.h
parent941b77a3b6946dd6223a029007f695aa841b6d34 (diff)
downloadop-kernel-dev-ef1872ec652b3bc472d6c0995d0b64d5058878ea.zip
op-kernel-dev-ef1872ec652b3bc472d6c0995d0b64d5058878ea.tar.gz
DMAENGINE: ste_dma40: only write phy channel config first time
We only need to write the configuration to a physical channel if it is free, else it is already written. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ste_dma40_ll.h')
-rw-r--r--drivers/dma/ste_dma40_ll.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index 2029280..c081f28 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -13,6 +13,9 @@
#define D40_DREG_PCDELTA (8 * 4)
#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
+#define D40_LCPA_CHAN_SIZE 32
+#define D40_LCPA_CHAN_DST_DELTA 16
+
#define D40_TYPE_TO_GROUP(type) (type / 16)
#define D40_TYPE_TO_EVENT(type) (type % 16)
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