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authorDave Jiang <dave.jiang@intel.com>2012-11-27 15:16:08 -0700
committerVinod Koul <vinod.koul@intel.com>2013-01-07 22:05:13 -0800
commit6decffd5f6afaf55722d9c85b8739621dca63d0f (patch)
tree42125cf2b650a00117c8d4354622898f6412bba0 /drivers/dma/ioat
parent1a363068dcc2269931daef360ed14d2a262f19f7 (diff)
downloadop-kernel-dev-6decffd5f6afaf55722d9c85b8739621dca63d0f.zip
op-kernel-dev-6decffd5f6afaf55722d9c85b8739621dca63d0f.tar.gz
ioat: remove chanerr mask setting for IOAT v3.x
The existing code set a value in the PCI_CHANERRMSK_INT register for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Dan Williams <djbw@fb.com>
Diffstat (limited to 'drivers/dma/ioat')
-rw-r--r--drivers/dma/ioat/dma_v3.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index 9d6f3bb..e52cf1e 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -1168,12 +1168,7 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
- /* -= IOAT ver.3 workarounds =- */
- /* Write CHANERRMSK_INT with 3E07h to mask out the errors
- * that can cause stability issues for IOAT ver.3, and clear any
- * pending errors
- */
- pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
+ /* clear any pending errors */
err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
if (err) {
dev_err(&pdev->dev, "channel error register unreachable\n");
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