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author | Tejun Heo <tj@kernel.org> | 2012-11-06 12:26:23 -0800 |
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committer | Tejun Heo <tj@kernel.org> | 2012-11-06 12:26:23 -0800 |
commit | 5b805f2a7675634fbdf9ac1c9b2256905ab2ea68 (patch) | |
tree | ee00d1e3d757458d66209b926d274491c6c3f61c /drivers/dma/dw_dmac_regs.h | |
parent | 1db1e31b1ee3ae126ef98f39083b5f213c7b41bf (diff) | |
parent | 201e72acb2d3821e2de9ce6091e98859c316b29a (diff) | |
download | op-kernel-dev-5b805f2a7675634fbdf9ac1c9b2256905ab2ea68.zip op-kernel-dev-5b805f2a7675634fbdf9ac1c9b2256905ab2ea68.tar.gz |
Merge branch 'cgroup/for-3.7-fixes' into cgroup/for-3.8
This is to receive device_cgroup fixes so that further device_cgroup
changes can be made in cgroup/for-3.8.
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/dma/dw_dmac_regs.h')
-rw-r--r-- | drivers/dma/dw_dmac_regs.h | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h index ff39fa6..8896559 100644 --- a/drivers/dma/dw_dmac_regs.h +++ b/drivers/dma/dw_dmac_regs.h @@ -98,9 +98,17 @@ struct dw_dma_regs { u32 DW_PARAMS; }; +#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO +#define dma_readl_native ioread32be +#define dma_writel_native iowrite32be +#else +#define dma_readl_native readl +#define dma_writel_native writel +#endif + /* To access the registers in early stage of probe */ #define dma_read_byaddr(addr, name) \ - readl((addr) + offsetof(struct dw_dma_regs, name)) + dma_readl_native((addr) + offsetof(struct dw_dma_regs, name)) /* Bitfields in DW_PARAMS */ #define DW_PARAMS_NR_CHAN 8 /* number of channels */ @@ -216,9 +224,9 @@ __dwc_regs(struct dw_dma_chan *dwc) } #define channel_readl(dwc, name) \ - readl(&(__dwc_regs(dwc)->name)) + dma_readl_native(&(__dwc_regs(dwc)->name)) #define channel_writel(dwc, name, val) \ - writel((val), &(__dwc_regs(dwc)->name)) + dma_writel_native((val), &(__dwc_regs(dwc)->name)) static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) { @@ -246,9 +254,9 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) } #define dma_readl(dw, name) \ - readl(&(__dw_regs(dw)->name)) + dma_readl_native(&(__dw_regs(dw)->name)) #define dma_writel(dw, name, val) \ - writel((val), &(__dw_regs(dw)->name)) + dma_writel_native((val), &(__dw_regs(dw)->name)) #define channel_set_bit(dw, reg, mask) \ dma_writel(dw, reg, ((mask) << 8) | (mask)) |