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authorOctavian Purdila <octavian.purdila@nxp.com>2017-05-30 18:57:18 +0300
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-06-24 01:35:13 +0200
commit3fafb4e77279ed375077e95f54ee687b481c24d2 (patch)
treee901fa7bc0da07297acd1532c47c3f4de5297698 /drivers/cpufreq
parenta0df77348ab37687c9513bc2dd772cbc6eadbe63 (diff)
downloadop-kernel-dev-3fafb4e77279ed375077e95f54ee687b481c24d2.zip
op-kernel-dev-3fafb4e77279ed375077e95f54ee687b481c24d2.tar.gz
cpufreq: imx6q: imx6ull should use the same flow as imx6ul
This fixes an issue with imx6ull where setting the frequency to 528Mhz would actually set the ARM clock to 324Mhz. Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r--drivers/cpufreq/imx6q-cpufreq.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 9c13f09..b6edd3c 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -101,7 +101,8 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
* - Disable pll2_pfd2_396m_clk
*/
- if (of_machine_is_compatible("fsl,imx6ul")) {
+ if (of_machine_is_compatible("fsl,imx6ul") ||
+ of_machine_is_compatible("fsl,imx6ull")) {
/*
* When changing pll1_sw_clk's parent to pll1_sys_clk,
* CPU may run at higher than 528MHz, this will lead to
@@ -215,7 +216,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
goto put_clk;
}
- if (of_machine_is_compatible("fsl,imx6ul")) {
+ if (of_machine_is_compatible("fsl,imx6ul") ||
+ of_machine_is_compatible("fsl,imx6ull")) {
pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
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