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authorMarc Zyngier <marc.zyngier@arm.com>2016-08-01 10:54:15 +0100
committerThomas Gleixner <tglx@linutronix.de>2016-08-01 16:15:53 +0200
commitf005bd7e3b84a353475a2895e2c7686a66297d87 (patch)
tree52b96cd02ae8bb5a9ad7bced1c5af49b1b6d2959 /drivers/clocksource
parentd761f3ed6e71bcca724a6e9e39efcac65b7b4ac1 (diff)
downloadop-kernel-dev-f005bd7e3b84a353475a2895e2c7686a66297d87.zip
op-kernel-dev-f005bd7e3b84a353475a2895e2c7686a66297d87.tar.gz
clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered
The ARM architected timer produces level-triggered interrupts (this is mandated by the architecture). Unfortunately, a number of device-trees get this wrong, and expose an edge-triggered interrupt. Until now, this wasn't too much an issue, as the programming of the trigger would fail (the corresponding PPI cannot be reconfigured), and the kernel would be happy with this. But we're about to change this, and trust DT a lot if the driver doesn't provide its own trigger information. In that context, the timer breaks badly. While we do need to fix the DTs, there is also some userspace out there (kvmtool) that generates the same kind of broken DT on the fly, and that will completely break with newer kernels. As a safety measure, and to keep buggy software alive as well as buying us some time to fix DTs all over the place, let's check what trigger configuration has been given us by the firmware. If this is not a level configuration, then we know that the DT/ACPI configuration is bust, and we pick some defaults which won't be worse than the existing setup. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Liu Gang <Gang.Liu@nxp.com> Cc: Mark Rutland <marc.rutland@arm.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Wenbin Song <Wenbin.Song@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Jon Hunter <jonathanh@nvidia.com> Cc: arm@kernel.org Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-arm-kernel@lists.infradead.org Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Ray Jui <rjui@broadcom.com> Cc: "Hou Zhiqiang" <B48286@freescale.com> Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com> Cc: linux-samsung-soc@vger.kernel.org Cc: Yuan Yao <yao.yuan@nxp.com> Cc: Jan Glauber <jglauber@cavium.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: linux-amlogic@lists.infradead.org Cc: soren.brinkmann@xilinx.com Cc: Rajesh Bhagat <rajesh.bhagat@freescale.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Duc Dang <dhdang@apm.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Carlo Caione <carlo@caione.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Link: http://lkml.kernel.org/r/1470045256-9032-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/arm_arch_timer.c26
1 files changed, 23 insertions, 3 deletions
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 28bce3f..5770054 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -8,6 +8,9 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+
+#define pr_fmt(fmt) "arm_arch_timer: " fmt
+
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
@@ -370,16 +373,33 @@ static bool arch_timer_has_nonsecure_ppi(void)
arch_timer_ppi[PHYS_NONSECURE_PPI]);
}
+static u32 check_ppi_trigger(int irq)
+{
+ u32 flags = irq_get_trigger_type(irq);
+
+ if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
+ pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
+ pr_warn("WARNING: Please fix your firmware\n");
+ flags = IRQF_TRIGGER_LOW;
+ }
+
+ return flags;
+}
+
static int arch_timer_starting_cpu(unsigned int cpu)
{
struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
+ u32 flags;
__arch_timer_setup(ARCH_CP15_TIMER, clk);
- enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], 0);
+ flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
+ enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
- if (arch_timer_has_nonsecure_ppi())
- enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
+ if (arch_timer_has_nonsecure_ppi()) {
+ flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+ enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags);
+ }
arch_counter_set_user_access();
if (evtstrm_enable)
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