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author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 13:51:19 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 13:51:19 -0700 |
commit | dfc25e4503aef6b82a1de4a0fbe19aafa8648fbe (patch) | |
tree | 0a4f3a07e2286918298e635186e42726f4658cbd /drivers/clocksource/timer-prima2.c | |
parent | 9f800363bb0ea459e15bef0928a72c88d374e489 (diff) | |
parent | 8f881c67368f82d0e20e1072b50b21132cc2440d (diff) | |
download | op-kernel-dev-dfc25e4503aef6b82a1de4a0fbe19aafa8648fbe.zip op-kernel-dev-dfc25e4503aef6b82a1de4a0fbe19aafa8648fbe.tar.gz |
Merge tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann:
"These cleanup patches are mainly move stuff around and should all be
harmless. They are mainly split out so that other branches can be
based on top to avoid conflicts.
Notable changes are:
- We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used (Uwe Kleine-König)
- The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions (Kumar Gala)
- A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
- Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
- mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
- at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people)"
* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
ARM: hisi: select HAVE_ARM_SCU only for SMP
ARM: efm32: allow uncompress debug output
ARM: prima2: build reset code standalone
ARM: at91: add PWM clock
ARM: at91: move sam9261 SoC to common clk
ARM: at91: prepare common clk transition for sam9261 SoC
ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
ARM: at91: dt: Add at91sam9261 dt SoC support
ARM: at91: switch sam9rl to common clock framework
ARM: at91/dt: define main clk frequency of at91sam9rlek
ARM: at91/dt: define at91sam9rl clocks
ARM: at91: prepare common clk transition for sam9rl SoCs
ARM: at91: prepare sam9 dt boards transition to common clk
ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
ARM: at91: Add at91sam9rl DT SoC support
ARM: at91: prepare at91sam9rl DT transition
ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
...
Diffstat (limited to 'drivers/clocksource/timer-prima2.c')
-rw-r--r-- | drivers/clocksource/timer-prima2.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/clocksource/timer-prima2.c b/drivers/clocksource/timer-prima2.c index 8a492d3..1a6b2d6 100644 --- a/drivers/clocksource/timer-prima2.c +++ b/drivers/clocksource/timer-prima2.c @@ -21,6 +21,8 @@ #include <linux/sched_clock.h> #include <asm/mach/time.h> +#define PRIMA2_CLOCK_FREQ 1000000 + #define SIRFSOC_TIMER_COUNTER_LO 0x0000 #define SIRFSOC_TIMER_COUNTER_HI 0x0004 #define SIRFSOC_TIMER_MATCH_0 0x0008 @@ -173,7 +175,7 @@ static u64 notrace sirfsoc_read_sched_clock(void) static void __init sirfsoc_clockevent_init(void) { sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE, + clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ, 2, -2); } @@ -190,8 +192,8 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np) rate = clk_get_rate(clk); - BUG_ON(rate < CLOCK_TICK_RATE); - BUG_ON(rate % CLOCK_TICK_RATE); + BUG_ON(rate < PRIMA2_CLOCK_FREQ); + BUG_ON(rate % PRIMA2_CLOCK_FREQ); sirfsoc_timer_base = of_iomap(np, 0); if (!sirfsoc_timer_base) @@ -199,14 +201,16 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np) sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); - writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); + writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1, + sirfsoc_timer_base + SIRFSOC_TIMER_DIV); writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); + BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, + PRIMA2_CLOCK_FREQ)); - sched_clock_register(sirfsoc_read_sched_clock, 64, CLOCK_TICK_RATE); + sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ); BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); |