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authorDmitry Osipenko <digetx@gmail.com>2018-05-08 19:26:03 +0300
committerThierry Reding <treding@nvidia.com>2018-05-18 12:34:49 +0200
commit08a52593fc0dca4b798f9a222cfbc827d008c1bf (patch)
tree6815250d3996f54582c26c306b828361a4c5cdb8 /drivers/clk
parent60cc43fc888428bb2f18f08997432d426a243338 (diff)
downloadop-kernel-dev-08a52593fc0dca4b798f9a222cfbc827d008c1bf.zip
op-kernel-dev-08a52593fc0dca4b798f9a222cfbc827d008c1bf.tar.gz
clk: tegra20: Add DEV1/DEV2 OSC dividers
CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 0ee56dd..ad5a7b5 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -26,6 +26,8 @@
#include "clk.h"
#include "clk-id.h"
+#define MISC_CLK_ENB 0x48
+
#define OSC_CTRL 0x50
#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
@@ -831,6 +833,18 @@ static void __init tegra20_periph_clk_init(void)
periph_clk_enb_refcnt);
clks[TEGRA20_CLK_PEX] = clk;
+ /* dev1 OSC divider */
+ clk_register_divider(NULL, "dev1_osc_div", "clk_m",
+ 0, clk_base + MISC_CLK_ENB, 22, 2,
+ CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
+ NULL);
+
+ /* dev2 OSC divider */
+ clk_register_divider(NULL, "dev2_osc_div", "clk_m",
+ 0, clk_base + MISC_CLK_ENB, 20, 2,
+ CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
+ NULL);
+
/* cdev1 */
clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);
clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
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