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| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2016-12-01 22:00:20 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-12-08 15:06:18 -0800 |
| commit | d86d46af84855403c00018be1c3e7bc190f2a6cd (patch) | |
| tree | c77aaa773d62b471a580c26fd35f28050efe9aa2 /drivers/clk | |
| parent | 155e8b3b0ee320ae866b97dd31eba8a1f080a772 (diff) | |
| download | op-kernel-dev-d86d46af84855403c00018be1c3e7bc190f2a6cd.zip op-kernel-dev-d86d46af84855403c00018be1c3e7bc190f2a6cd.tar.gz | |
clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock
The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/bcm/clk-bcm2835.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index df96fe6..eaf82f4 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + /* + * Allow rate change propagation only on PLLH_AUX which is + * assigned index 7 in the parent array. + */ + .set_rate_parent = BIT(7)), /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( |
