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author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-01-25 19:19:08 +0100 |
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committer | Jason Cooper <jason@lakedaemon.net> | 2014-02-06 18:06:50 +0000 |
commit | 0a11a6ae94373f37e738f7dc8f51d60a78d78a58 (patch) | |
tree | 071c2f0e394865a0bc1ff75768775cef41d3dc59 /drivers/clk | |
parent | 07ad6836fa21b8ae1715d5f82a0d28c4140e1e73 (diff) | |
download | op-kernel-dev-0a11a6ae94373f37e738f7dc8f51d60a78d78a58.zip op-kernel-dev-0a11a6ae94373f37e738f7dc8f51d60a78d78a58.tar.gz |
clk: mvebu: armada-xp: maintain clock init order
Init order of CLK_OF_DECLARE'd drivers depends on compile order.
Unfortunately, clk_of_init does not allow drivers to return errors,
e.g. -EPROBE_DEFER if parent clocks have not been registered, yet.
To avoid init order woes for MVEBU clock drivers, we take care of
proper init order ourselves. This patch joins core-clk and gating-clk
init to maintain proper init order.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/mvebu/armada-xp.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c index 9922c44..b309431 100644 --- a/drivers/clk/mvebu/armada-xp.c +++ b/drivers/clk/mvebu/armada-xp.c @@ -158,13 +158,6 @@ static const struct coreclk_soc_desc axp_coreclks = { .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), }; -static void __init axp_coreclk_init(struct device_node *np) -{ - mvebu_coreclk_setup(np, &axp_coreclks); -} -CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock", - axp_coreclk_init); - /* * Clock Gating Control */ @@ -202,9 +195,14 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = { { } }; -static void __init axp_clk_gating_init(struct device_node *np) +static void __init axp_clk_init(struct device_node *np) { - mvebu_clk_gating_setup(np, axp_gating_desc); + struct device_node *cgnp = + of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock"); + + mvebu_coreclk_setup(np, &axp_coreclks); + + if (cgnp) + mvebu_clk_gating_setup(cgnp, axp_gating_desc); } -CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock", - axp_clk_gating_init); +CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init); |