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authorMike Turquette <mturquette@linaro.org>2013-04-11 11:31:37 -0700
committerMike Turquette <mturquette@linaro.org>2013-04-12 11:23:24 -0700
commitf363e215931ecc8077b6f6ee6d39d9ffaf1c3bd0 (patch)
tree737e5e9ccd32fc757d7435af3e0b0ba0b9cda7bf /drivers/clk
parentd3a1c7be8361e2fbb6affbdb19de47ca48d6c402 (diff)
downloadop-kernel-dev-f363e215931ecc8077b6f6ee6d39d9ffaf1c3bd0.zip
op-kernel-dev-f363e215931ecc8077b6f6ee6d39d9ffaf1c3bd0.tar.gz
clk: composite: allow fixed rates & fixed dividers
The composite clock assumes that any clock implementing the .recalc_rate callback will also implement .round_rate and .set_rate. This is not always true; the basic fixed-rate clock will only implement .recalc_rate and a fixed-divider clock may choose to implement .recalc_rate and .round_rate but not .set_rate. Fix this by conditionally registering .round_rate and .set_rate callbacks based on the rate_ops passed in to clk_composite_register. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-composite.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 6f4728c6..a33f46f 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -150,17 +150,26 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
}
if (rate_hw && rate_ops) {
- if (!rate_ops->recalc_rate || !rate_ops->round_rate ||
- !rate_ops->set_rate) {
+ if (!rate_ops->recalc_rate) {
clk = ERR_PTR(-EINVAL);
goto err;
}
+ /* .round_rate is a prerequisite for .set_rate */
+ if (rate_ops->round_rate) {
+ clk_composite_ops->round_rate = clk_composite_round_rate;
+ if (rate_ops->set_rate) {
+ clk_composite_ops->set_rate = clk_composite_set_rate;
+ }
+ } else {
+ WARN(rate_ops->set_rate,
+ "%s: missing round_rate op is required\n",
+ __func__);
+ }
+
composite->rate_hw = rate_hw;
composite->rate_ops = rate_ops;
clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
- clk_composite_ops->round_rate = clk_composite_round_rate;
- clk_composite_ops->set_rate = clk_composite_set_rate;
}
if (gate_hw && gate_ops) {
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