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authorAlexandre Courbot <acourbot@nvidia.com>2013-05-26 11:56:31 +0900
committerMike Turquette <mturquette@linaro.org>2013-05-31 12:24:36 -0700
commit9139227d4caef6a8daae8a428f9a4bbb7394ea8b (patch)
tree95ef761c681574c4a6e59cc352bf9d85cbaa6498 /drivers/clk
parent995968e40e74ddf678e8b8312865d7400708d893 (diff)
downloadop-kernel-dev-9139227d4caef6a8daae8a428f9a4bbb7394ea8b.zip
op-kernel-dev-9139227d4caef6a8daae8a428f9a4bbb7394ea8b.tar.gz
clk: tegra114: correctly output clk_32k
Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra114.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 6574f36..772fc2e 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -127,6 +127,7 @@
#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
#define PMC_CTRL 0
#define PMC_CTRL_BLINK_ENB 7
+#define PMC_BLINK_TIMER 0x40
#define OSC_CTRL 0x50
#define OSC_CTRL_OSC_FREQ_SHIFT 28
@@ -1625,6 +1626,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
clks[clk_out_3] = clk;
/* blink */
+ /* clear the blink timer register to directly output clk_32k */
+ writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
pmc_base + PMC_DPD_PADS_ORIDE,
PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
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