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| author | Zheng Yang <zhengyang@rock-chips.com> | 2017-05-25 18:00:24 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-02-12 15:00:55 +0100 |
| commit | 36ec03618c12ad3308f7a80994ee4b2129a1e381 (patch) | |
| tree | 46a668cda737373fcb9e0214d7c3a08b67ca09b5 /drivers/clk | |
| parent | 7f872cb362d312b0b75975441b3717253e323b81 (diff) | |
| download | op-kernel-dev-36ec03618c12ad3308f7a80994ee4b2129a1e381.zip op-kernel-dev-36ec03618c12ad3308f7a80994ee4b2129a1e381.tar.gz | |
clk: rockchip: add flags for rk3328 dclk_lcdc
dclk_lcdc can be sourced from a general pll source as well
as the hdmiphy's pll output. We will want to set this source
by hand (to the system-pll-source in most cases) and also
want rate changes to this clock to be able to also touch
the pll source clock if needed, so add CLK_SET_RATE_PARENT
and CLK_SET_RATE_NO_REPARENT for dclk_lcdc.
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
[ammended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3328.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 983ad57..f680b42 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { RK3328_CLKGATE_CON(5), 6, GFLAGS), DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0, RK3328_CLKSEL_CON(40), 3, 3, DFLAGS), - MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, 0, + MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3328_CLKSEL_CON(40), 1, 1, MFLAGS), /* |
