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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-07-25 21:06:56 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2013-08-26 10:58:21 +0200
commit1fb2e4aab8b31b15e6be5debacb4203333360fd2 (patch)
treeab19fee3cc118d0205aa5bcc937be601cd671381 /drivers/clk
parent6a721db180a22d8e2d59d864446309bc7a09c26f (diff)
downloadop-kernel-dev-1fb2e4aab8b31b15e6be5debacb4203333360fd2.zip
op-kernel-dev-1fb2e4aab8b31b15e6be5debacb4203333360fd2.tar.gz
clk: sunxi: Add Allwinner A20 gates
The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6fd0204..d39f213 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -463,6 +463,10 @@ static const __initconst struct gates_data sun6i_a31_ahb1_gates_data = {
.mask = {0xEDFE7F62, 0x794F931},
};
+static const __initconst struct gates_data sun7i_a20_ahb_gates_data = {
+ .mask = { 0x12f77fff, 0x16ff3f },
+};
+
static const __initconst struct gates_data sun4i_apb0_gates_data = {
.mask = {0x4EF},
};
@@ -475,6 +479,10 @@ static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
.mask = {0x61},
};
+static const __initconst struct gates_data sun7i_a20_apb0_gates_data = {
+ .mask = { 0x4ff },
+};
+
static const __initconst struct gates_data sun4i_apb1_gates_data = {
.mask = {0xFF00F7},
};
@@ -495,6 +503,10 @@ static const __initconst struct gates_data sun6i_a31_apb2_gates_data = {
.mask = {0x3F000F},
};
+static const __initconst struct gates_data sun7i_a20_apb1_gates_data = {
+ .mask = { 0xff80ff },
+};
+
static void __init sunxi_gates_clk_setup(struct device_node *node,
struct gates_data *data)
{
@@ -576,13 +588,16 @@ static const __initconst struct of_device_id clk_gates_match[] = {
{.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
+ {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
+ {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
+ {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
{}
};
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