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| author | Thierry Reding <treding@nvidia.com> | 2016-06-21 17:30:35 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-06-22 13:46:52 +0200 |
| commit | 2858038696b9672ef50cd38904fec510bc814584 (patch) | |
| tree | e84f445c95a083bc3203dd9f364eecfeb1e8ccc8 /drivers/clk/tegra | |
| parent | e452b818db48dc2c7edb5afd62de47ae0363aec2 (diff) | |
| download | op-kernel-dev-2858038696b9672ef50cd38904fec510bc814584.zip op-kernel-dev-2858038696b9672ef50cd38904fec510bc814584.tar.gz | |
clk: tegra: Mark timer clock as critical
The timer clock feeds the timer block, which, among other things, is
used to drive the SOR lane sequencer. Since the Tegra timer driver is
not enabled on 64-bit ARM, nothing currently claims that clock and it
gets disabled by the common clock framework at late_init time.
Given the non-obvious dependencies, the timer clock can be considered
a critical part of the SoC infrastructure, requiring its clock source
to be always on.
Acked-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-periph.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index af85c8a..4ce4e7f 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = { static struct tegra_periph_init_data gate_clks[] = { GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), - GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), + GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), |
