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authorJon Hunter <jonathanh@nvidia.com>2015-12-04 17:04:23 +0000
committerThierry Reding <treding@nvidia.com>2016-02-02 15:49:32 +0100
commitd9e657919afe0794713b5ffb069f9f66c37bfe17 (patch)
tree30fd2a9f85cf99e3fe3b06b3d4c0a14f9e14e119 /drivers/clk/tegra
parent2d5b6cf84a1764aa9837128bc1e6fd53cb0bb9c1 (diff)
downloadop-kernel-dev-d9e657919afe0794713b5ffb069f9f66c37bfe17.zip
op-kernel-dev-d9e657919afe0794713b5ffb069f9f66c37bfe17.tar.gz
clk: tegra: Fix sparse warning for pll_m
Sparse generates the following warning for the pll_m params structure: drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry defined twice drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here Fix this by correcting the index for the MISC1 register. Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk-tegra210.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index ca04c2d8..271ea15 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -1566,7 +1566,7 @@ static struct tegra_clk_pll_params pll_m_params = {
.iddq_bit_idx = PLLM_IDDQ_BIT,
.max_p = PLL_QLIN_PDIV_MAX,
.ext_misc_reg[0] = PLLM_MISC2,
- .ext_misc_reg[0] = PLLM_MISC1,
+ .ext_misc_reg[1] = PLLM_MISC1,
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
.pdiv_tohw = pll_qlin_pdiv_to_hw,
.div_nmp = &pllm_nmp,
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