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author | NeilBrown <neilb@suse.com> | 2015-09-05 11:07:04 +0200 |
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committer | NeilBrown <neilb@suse.com> | 2015-09-05 11:08:32 +0200 |
commit | e89c6fdf9e0eb1b5a03574d4ca73e83eae8deb91 (patch) | |
tree | f9df292ed03a5a3c4ddc658ae3646f02a1ffafce /drivers/clk/tegra/cvb.h | |
parent | c3cce6cda162eb2b2960a85d9c8992f4f3be85d0 (diff) | |
parent | 1081230b748de8f03f37f80c53dfa89feda9b8de (diff) | |
download | op-kernel-dev-e89c6fdf9e0eb1b5a03574d4ca73e83eae8deb91.zip op-kernel-dev-e89c6fdf9e0eb1b5a03574d4ca73e83eae8deb91.tar.gz |
Merge linux-block/for-4.3/core into md/for-linux
There were a few conflicts that are fairly easy to resolve.
Signed-off-by: NeilBrown <neilb@suse.com>
Diffstat (limited to 'drivers/clk/tegra/cvb.h')
-rw-r--r-- | drivers/clk/tegra/cvb.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h new file mode 100644 index 0000000..f62cdc4 --- /dev/null +++ b/drivers/clk/tegra/cvb.h @@ -0,0 +1,67 @@ +/* + * Utility functions for parsing Tegra CVB voltage tables + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __DRIVERS_CLK_TEGRA_CVB_H +#define __DRIVERS_CLK_TEGRA_CVB_H + +#include <linux/types.h> + +struct device; + +#define MAX_DVFS_FREQS 40 + +struct rail_alignment { + int offset_uv; + int step_uv; +}; + +struct cvb_coefficients { + int c0; + int c1; + int c2; +}; + +struct cvb_table_freq_entry { + unsigned long freq; + struct cvb_coefficients coefficients; +}; + +struct cvb_cpu_dfll_data { + u32 tune0_low; + u32 tune0_high; + u32 tune1; +}; + +struct cvb_table { + int speedo_id; + int process_id; + + int min_millivolts; + int max_millivolts; + struct rail_alignment alignment; + + int speedo_scale; + int voltage_scale; + struct cvb_table_freq_entry cvb_table[MAX_DVFS_FREQS]; + struct cvb_cpu_dfll_data cpu_dfll_data; +}; + +const struct cvb_table *tegra_cvb_build_opp_table( + const struct cvb_table *cvb_tables, + size_t sz, int process_id, + int speedo_id, int speedo_value, + unsigned long max_rate, + struct device *opp_dev); + +#endif |