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| author | Thierry Reding <treding@nvidia.com> | 2016-04-08 15:09:56 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:53 +0200 |
| commit | e8f6a68c508b5d1cc4612ada028d87c74ab279d5 (patch) | |
| tree | 47e8213aaf6ea3bf7286aa0eba891db80952824e /drivers/clk/tegra/cvb.h | |
| parent | 27ed2f7e7ca5c38a8ce695e58e6cf270c26f370b (diff) | |
| download | op-kernel-dev-e8f6a68c508b5d1cc4612ada028d87c74ab279d5.zip op-kernel-dev-e8f6a68c508b5d1cc4612ada028d87c74ab279d5.tar.gz | |
clk: tegra: dfll: Make code more comprehensible
Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/cvb.h')
| -rw-r--r-- | drivers/clk/tegra/cvb.h | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index f62cdc4..e6bf858 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -53,15 +53,13 @@ struct cvb_table { int speedo_scale; int voltage_scale; - struct cvb_table_freq_entry cvb_table[MAX_DVFS_FREQS]; + struct cvb_table_freq_entry entries[MAX_DVFS_FREQS]; struct cvb_cpu_dfll_data cpu_dfll_data; }; -const struct cvb_table *tegra_cvb_build_opp_table( - const struct cvb_table *cvb_tables, - size_t sz, int process_id, - int speedo_id, int speedo_value, - unsigned long max_rate, - struct device *opp_dev); +const struct cvb_table * +tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables, + size_t count, int process_id, int speedo_id, + int speedo_value, unsigned long max_freq); #endif |
