diff options
| author | Thierry Reding <thierry.reding@avionic-design.de> | 2013-03-14 16:27:05 +0100 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-04-01 11:44:38 -0700 |
| commit | 0f1bc12e9eddaba2baf52d020d37670dbabe3702 (patch) | |
| tree | 7236ae7d234d20f2dacefd1fb8814d06cb57cdc2 /drivers/clk/tegra/clk-tegra20.c | |
| parent | 07961ac7c0ee8b546658717034fe692fd12eefa9 (diff) | |
| download | op-kernel-dev-0f1bc12e9eddaba2baf52d020d37670dbabe3702.zip op-kernel-dev-0f1bc12e9eddaba2baf52d020d37670dbabe3702.tar.gz | |
clk: tegra: Allow PLLE training to succeed
Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 1e2de73..f873dce 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -703,7 +703,7 @@ static void tegra20_pll_init(void) clks[pll_a_out0] = clk; /* PLLE */ - clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL, + clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 0, 100000000, &pll_e_params, 0, pll_e_freq_table, NULL); clk_register_clkdev(clk, "pll_e", NULL); |
