diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-02-12 20:47:59 +0530 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-02-13 11:17:03 -0700 |
| commit | 527fad1bc519df8eedd397482febb51526e5d987 (patch) | |
| tree | 003feaff3289f9d27292d2332710e951f142ea25 /drivers/clk/tegra/clk-tegra20.c | |
| parent | 8364f5d96509e206f02a74bbdc2d4e3742cdefe4 (diff) | |
| download | op-kernel-dev-527fad1bc519df8eedd397482febb51526e5d987.zip op-kernel-dev-527fad1bc519df8eedd397482febb51526e5d987.tar.gz | |
clk: tegra: initialise parent of uart clocks
Initialise the parent of UARTs to PLLP and disabling clock by
default.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3d70634..143ce1f 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1254,8 +1254,11 @@ static __initdata struct tegra_clk_init_table init_table[] = { {csite, clk_max, 0, 1}, {emc, clk_max, 0, 1}, {cclk, clk_max, 0, 1}, - {uarta, pll_p, 0, 1}, - {uartd, pll_p, 0, 1}, + {uarta, pll_p, 0, 0}, + {uartb, pll_p, 0, 0}, + {uartc, pll_p, 0, 0}, + {uartd, pll_p, 0, 0}, + {uarte, pll_p, 0, 0}, {usbd, clk_max, 12000000, 0}, {usb2, clk_max, 12000000, 0}, {usb3, clk_max, 12000000, 0}, |
