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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-04-03 17:40:39 +0300 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-04-04 16:10:45 -0600 |
| commit | 0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f (patch) | |
| tree | 989c920b532d4d5d7372c275ed828356cff9c581 /drivers/clk/tegra/clk-tegra20.c | |
| parent | 7ba28813b41120dd67329fd04dc732ea7fef05a0 (diff) | |
| download | op-kernel-dev-0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f.zip op-kernel-dev-0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f.tar.gz | |
clk: tegra: Add PLL post divider table
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index c2a1c4c..f215bf1 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -441,6 +441,12 @@ static struct tegra_clk_pll_params pll_d_params = { .lock_delay = 1000, }; +static struct pdiv_map pllu_p[] = { + { .pdiv = 1, .hw_val = 1 }, + { .pdiv = 2, .hw_val = 0 }, + { .pdiv = 0, .hw_val = 0 }, +}; + static struct tegra_clk_pll_params pll_u_params = { .input_min = 2000000, .input_max = 40000000, @@ -453,6 +459,7 @@ static struct tegra_clk_pll_params pll_u_params = { .lock_bit_idx = PLL_BASE_LOCK, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_delay = 1000, + .pdiv_tohw = pllu_p, }; static struct tegra_clk_pll_params pll_x_params = { |
