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author | Chen-Yu Tsai <wens@csie.org> | 2014-09-06 14:45:10 +0800 |
---|---|---|
committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-09-13 10:07:24 +0200 |
commit | cfe4c93b58924b3764cd7269d3d953049405e938 (patch) | |
tree | 915e04f56e9f9a243e9862100763c4fcca2284c4 /drivers/clk/sunxi | |
parent | 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9 (diff) | |
download | op-kernel-dev-cfe4c93b58924b3764cd7269d3d953049405e938.zip op-kernel-dev-cfe4c93b58924b3764cd7269d3d953049405e938.tar.gz |
clk: sunxi: add correct divider table for sun4i-apb0 clock
The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.
This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.
This patch adds a proper divider table for it, so the correct
clock rate can be calculated.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi')
-rw-r--r-- | drivers/clk/sunxi/clk-sunxi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index b654b7b..2cf6581 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -762,10 +762,19 @@ static const struct div_data sun4i_ahb_data __initconst = { .width = 2, }; +static const struct clk_div_table sun4i_apb0_table[] __initconst = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { } /* sentinel */ +}; + static const struct div_data sun4i_apb0_data __initconst = { .shift = 8, .pow = 1, .width = 2, + .table = sun4i_apb0_table, }; static const struct div_data sun6i_a31_apb2_div_data __initconst = { |