diff options
| author | Dinh Nguyen <dinguyen@altera.com> | 2013-12-13 16:38:28 -0600 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-02-18 14:08:08 -0800 |
| commit | b7cec13f082fcc6e690559657d3f5493ea6eecb7 (patch) | |
| tree | ec9610445a8013733e869744d442a6b67dad0ab3 /drivers/clk/socfpga | |
| parent | 6a7e71221d4e6cd185a51e2659f279da67f2e22d (diff) | |
| download | op-kernel-dev-b7cec13f082fcc6e690559657d3f5493ea6eecb7.zip op-kernel-dev-b7cec13f082fcc6e690559657d3f5493ea6eecb7.tar.gz | |
clk: socfpga: Look for the GPIO_DB_CLK by its offset
After the patch:
"clk: socfpga: Map the clk manager base address in the clock driver"
The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace
looking for the GPIO_DB_CLK by its divider offset instead.
Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as
this represents the GPIO_DB_CLK.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Diffstat (limited to 'drivers/clk/socfpga')
| -rw-r--r-- | drivers/clk/socfpga/clk.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 4fb52e1..cba21a0 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -51,7 +51,7 @@ #define SOCFPGA_NAND_CLK "nand_clk" #define SOCFPGA_NAND_X_CLK "nand_x_clk" #define SOCFPGA_MMC_CLK "sdmmc_clk" -#define SOCFPGA_DB_CLK "gpio_db_clk" +#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 #define div_mask(width) ((1 << (width)) - 1) #define streq(a, b) (strcmp((a), (b)) == 0) @@ -234,7 +234,8 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, else if (socfpgaclk->div_reg) { val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val &= div_mask(socfpgaclk->width); - if (streq(hwclk->init->name, SOCFPGA_DB_CLK)) + /* Check for GPIO_DB_CLK by its offset */ + if ((int)socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) div = val + 1; else div = (1 << val); |
