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| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2015-12-08 14:46:54 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-12-16 16:35:17 +0100 |
| commit | c0feb268da73ae3ede23ae60d6ccc551c4e93250 (patch) | |
| tree | 6b4bf20cd145c4984ebe9cf8a17d8530e6368a1c /drivers/clk/samsung/clk-exynos5420.c | |
| parent | 9f9499ae8e6415cefc4fe0a96ad0e27864353c89 (diff) | |
| download | op-kernel-dev-c0feb268da73ae3ede23ae60d6ccc551c4e93250.zip op-kernel-dev-c0feb268da73ae3ede23ae60d6ccc551c4e93250.tar.gz | |
clk: samsung: exynos542x: add missing parent GSCL block clocks
This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 389af3c..4bae2e3 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -677,8 +677,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP5, 20, 1), MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), - MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, - SRC_TOP5, 28, 1), + MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", + mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), @@ -729,8 +729,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP12, 20, 1), MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), - MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, - SRC_TOP12, 28, 1), + MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", + mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), /* DISP1 Block */ MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), |
