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| author | Chander Kashyap <chander.kashyap@linaro.org> | 2013-09-26 14:36:35 +0530 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-12-04 10:46:45 -0800 |
| commit | cdf64eeeb0d762585e2126f3024458d199c2635d (patch) | |
| tree | 425caea31cd6fd5d0fbdb5af7bae55dc9b6e82cf /drivers/clk/samsung/clk-exynos5420.c | |
| parent | 79ba3fdafdb5361e5158452ed6b1fca0bc39cbc8 (diff) | |
| download | op-kernel-dev-cdf64eeeb0d762585e2126f3024458d199c2635d.zip op-kernel-dev-cdf64eeeb0d762585e2126f3024458d199c2635d.tar.gz | |
clk: exynos5420: fix cpll clock register offsets
Fixes cpll control and lock register offset values for Exynos5420 SoC.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 48c4a93..87ea796 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -737,8 +737,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), - [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, - MPLL_CON0, NULL), + [cpll] = PLL(pll_2550, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK, + CPLL_CON0, NULL), [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK, DPLL_CON0, NULL), [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, |
