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authorMike Turquette <mturquette@linaro.org>2014-07-02 10:05:56 -0700
committerMike Turquette <mturquette@linaro.org>2014-07-02 10:05:56 -0700
commit4924b8a2fa137335bef82829733b30a5172e51b3 (patch)
treeb4475934e16fb14f1413f2a2892c732af420b1f4 /drivers/clk/samsung/clk-exynos5250.c
parent5c726dcdd22d2fa007a87e258128393acfc364d2 (diff)
parent44ff0254b89079a8a95e652635e760d93196ac1f (diff)
downloadop-kernel-dev-4924b8a2fa137335bef82829733b30a5172e51b3.zip
op-kernel-dev-4924b8a2fa137335bef82829733b30a5172e51b3.tar.gz
Merge tag 'for_3.16/samsung-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes-samsung
Samsung clock fixes for v3.16. This pull request contains fixes for various issues found while testing -rc versions of Linux 3.16. Mostly two kinds of patches: * Fixes of incorrectly defined clocks 1) a37c82a clk: samsung: exynos4: Remove SRC_MASK_ISP gates Issue present since v3.10. 2) 0b1643b clk/exynos5250: fix bit number for tv sysmmu clock Issue present since v3.16. 3) 44ff025 clk: exynos5420: Remove aclk66_peric from the clock tree description Issue present since v3.11. * Adding things missed by original patches 1) cec1cde clk: samsung: fix several typos to fix boot on s3c2410 2) 34ece9e clk: samsung: add more aliases for s3c24xx Both issues present since the driver was added in v3.16. 3) a92dda4 clk: s3c64xx: Hookup SPI clocks correctly Issue present since v3.12.
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5250.c')
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1fad4c5..184f642 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
- GATE_IP_DISP1, 2, 0, 0),
+ GATE_IP_DISP1, 9, 0, 0),
GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
GATE_IP_DISP1, 8, 0, 0),
GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
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