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| author | Heiko Stübner <heiko@sntech.de> | 2014-09-24 23:41:54 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-09-25 14:48:40 -0700 |
| commit | d1a559a1cb1d4aa1c63c56bdb39d9d18dfaf9523 (patch) | |
| tree | 21e507f9675f993517834df6e5870028a474277b /drivers/clk/rockchip | |
| parent | f9c0d14062e235ef11c9d5e776ebc7a05894f299 (diff) | |
| download | op-kernel-dev-d1a559a1cb1d4aa1c63c56bdb39d9d18dfaf9523.zip op-kernel-dev-d1a559a1cb1d4aa1c63c56bdb39d9d18dfaf9523.tar.gz | |
clk: rockchip: add missing rk3288 npll rate table
The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 2e1d790d..dcd3fac 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -143,7 +143,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), - RK3288_MODE_CON, 14, 9, NULL), + RK3288_MODE_CON, 14, 9, rk3288_pll_rates), }; static struct clk_div_table div_hclk_cpu_t[] = { |
